From July 17 to 20, the 2026 World Artificial Intelligence Conference and High-Level Meeting on Global AI Governance (WAIC 2026) opened simultaneously across “three zones and four venues” in Shanghai: the World Expo area, Zhangjiang, and West Bund.

Qiyi Moore, an industry-leading provider of full-stack AI networking interconnect products and solutions, made its first appearance at WAIC 2026.

During the conference, the company hosted the “Intelligent Connectivity as the Engine, Advancing Together as One: AI Networking Frontier Ecosystem Forum,” creating a platform for deeper dialogue on collaborative innovation across the AI networking interconnect ecosystem.

Leading research institutions and companies, including Shanghai AI Laboratory, the Hong Kong University of Science and Technology (Guangzhou), SenseTime, Biren Technology, DataCanvas, Sunrise Technology, Kehua Cloud, TuringQ, and Turing Core, joined a range of upstream and downstream ecosystem partners and industry guests at the event.

At the forum, an initiative to co-build a domestic supernode ecosystem was officially launched, alongside the release of the Co-Packaged Optics (CPO) Technology White Paper, underscoring Qiyi Moore’s forward-looking push for industry collaboration.

Qiyi Moore also showcased a set of core technologies and products, including its domestically built full-stack supernode interconnect solution, an IBGDA demo co-developed with Biren Technology for direct communication between domestic GPUs and domestic RDMA network cards, and next-generation optical interconnect collaboration results. Together, the exhibits highlighted the company’s technical progress and ecosystem work in computing power network interconnects, presenting global attendees with China’s capacity for independent innovation in AI computing power.

In his forum remarks, Qiyi Moore founder and chairman Tian Mochen said that only when trees grow into a forest can they withstand the wind. It is this understanding of “forming a connected forest,” he said, that has driven Qiyi Moore since its founding to serve as an active builder and connector of the AI networking interconnect ecosystem. “We know that network interconnects are the key pathways for breaking down computing power silos and linking individual strong points into an efficient system. No single company can complete the entire chain from underlying chips to top-level applications alone; only by expanding the ecosystem can companies become stronger.”

First Full-Stack Domestic Supernode Interconnect Solution Debuts, Linking System-Level Collaboration

The core challenge facing domestic computing power today is not that individual chips lag in performance, but a structural imbalance: strong single points and weak systems.

Chip performance keeps improving across vendors, but interconnects within chips, between chips, across networks, and between clusters remain fragmented, with no unified full-stack view or system-level coordination.

This long-running fragmentation directly prevents system-level performance from scaling linearly as chip counts rise, leaving computing power resources badly fragmented.

In the supernode era, where interconnects sit at the center, that weakness will be magnified many times over.

Qiyi Moore has long focused on AI networking interconnects. Its current product portfolio spans full-stack solutions from Scale-Out network-to-network interconnects and Scale-Up supernode XPU-to-XPU interconnects to next-generation optical interconnects.

Against this industry backdrop, Qiyi Moore used this year’s WAIC to debut its domestically built full-stack supernode interconnect solution. Presented through a supernode cabinet, the system offered a clear view of how domestic AI computing power infrastructure is moving from “single-chip breakthroughs” to “system-level collaborative optimization,” providing an independently controllable full-stack interconnect foundation for large-scale domestic AI computing power clusters.

Zhu Jundong, co-founder and vice president of products and solutions at Qiyi Moore, said the core value of the full-stack solution is that it gives domestic AI computing power an evolvable, collaborative, and non-locked-in system-level infrastructure. Chip vendors can flexibly build supernode systems on a unified foundation, upper-layer applications can gain seamless horizontal scalability, and the industrial ecosystem can move from isolated efforts toward a coordinated breakthrough. Domestic computing power is at a critical historical juncture, Zhu said, and interconnects are no longer a supporting role but the core lifeline that determines overall system efficiency. Qiyi Moore, he added, is willing to use open and efficient full-stack interconnect technologies to pave the way for China’s domestic AI industry.

IBGDA Demo: Deep Collaboration Between Domestic GPUs and RDMA Network Cards

The full-stack solution described above spans multiple layers from on-chip interconnects to network-to-network interconnects. One of its most practical technical validations is direct communication between domestic GPUs and domestic RDMA network cards, which is exactly the IBGDA solution jointly demonstrated by Qiyi Moore and Biren Technology.

In typical training or inference for MoE models, expert-parallel communication includes two core stages, Dispatch and Combine, each involving massive volumes of small-granularity data exchange.

In traditional cross-node communication, GPUs must route instructions through CPUs, creating additional latency and CPU overhead.

IBGDA technology bypasses CPU processing, sharply reducing waiting time for instruction relay and fully unlocking the throughput advantage of GPUs’ massive parallel-computing threads. In All-to-All communication scenarios, it delivers both higher throughput and lower latency.

In comparisons between international and domestic approaches, NVIDIA was first to implement an IBGDA solution through deep coordination between its GPUs and ConnectX network cards, providing mature latency-sensitive communication capabilities for large-scale AI inference scenarios.

For domestic clusters to deliver the same capability, domestic GPUs must first support NVSHMEM-like programming, the latest NCCL communication library, and collective communication libraries such as DeepEP, and then complete software and hardware adaptation with domestic RDMA network cards before efficient GPU-to-network-card direct communication can be achieved.

At present, however, domestic GPU support for IBGDA mainly remains limited to adaptation with NVIDIA network cards. Large-scale deployments of domestic GPUs directly connected to domestic RDMA network cards remain relatively rare, making this link a bottleneck for improving communication efficiency in domestic clusters.

That situation is starting to change. Qiyi Moore’s single-channel 400G RDMA ASIC engine, designed on the Kiwi SNIC 800G platform architecture, has completed coordinated software-hardware development. It is compatible with collective communication libraries optimized for MoE models, benchmarked against DeepEP, and natively supports the IBGDA mechanism, under which the GPU directly initiates communication.

At this year’s WAIC, Qiyi Moore and Biren Technology jointly demonstrated an IBGDA solution connecting domestic GPUs directly to domestic RDMA network cards.

The IBGDA demo test platform was benchmarked against NVIDIA IBGDA test data, and measured results reached a comparable level.

The test results show that IBGDA has a generational advantage over traditional IBRC in small-packet, high-frequency, tightly synchronized scenarios.

Bandwidth for a single small message rose sharply, with both raw small-packet sending and merged sending throughput achieving a qualitative leap. All-to-All communication latency was also cut significantly, approaching a twofold improvement.

Most importantly, the “small-packet penalty” in traditional solutions, where small-message latency far exceeds large-message latency, was completely eliminated.

The solution is built on an open Ethernet ecosystem. While retaining Ethernet’s advantages in flexible deployment and controllable cost, it gives domestic computing power clusters a Scale-Out networking option that combines high performance with autonomy.

The joint demonstration is technically significant. Through deep software-hardware coordination, it bypasses cumbersome protocol conversion, sharply reduces communication latency, and substantially improves the overall processing efficiency of AI inference clusters.

It is a vivid example of best practice for “domestic chips plus domestic networks,” and its measured data shows that China’s domestic computing power ecosystem already has practical capabilities for underlying interoperability and system-level collaborative optimization.

OSU Supernode Interconnect Chiplet Roadmap Targets Next-Generation Optical Interconnects

Another major highlight of the forum was the release of the Co-Packaged Optics (CPO) Technology White Paper, referred to below as the white paper.

The white paper was initiated by the Hong Kong University of Science and Technology (Guangzhou), with Qiyi Moore participating alongside Sunrise, Biren Technology, TuringQ, Singularity Photonics, and other organizations, bringing together collective insight from industry, academia, and research.

The white paper systematically reviews CPO’s technology roadmap, industrial challenges, and future evolution, providing authoritative guidance and practical reference for standardizing, scaling, and industrializing domestic optical interconnect technologies.

Looking ahead, optical interconnects are becoming the foundation of next-generation supernode systems.

Traditional electrical interconnects are constrained by the physical limits of copper cables, making bandwidth density and energy consumption increasingly unable to support next-generation computing power demand. Optical interconnects, by contrast, face almost no communication-distance anxiety within Scale-Up environments.

Today’s mainstream optical interconnects are dominated by pluggable optical modules, with optical engines still sitting at the edge of the motherboard.

To meet Scale-Up requirements for low power consumption and low latency, optical engines must keep moving closer to the compute core. This creates a clear evolution path: pluggable optical modules, NPO, CPO, and OIO, with the ultimate goal of “native optics,” meaning optical interconnect functions integrated directly inside compute chips.

Shorter paths deliver benefits beyond reduced physical distance. Closer interconnects can eliminate DSPs, effectively reducing latency while simplifying system design, cutting power consumption and cost, and ultimately improving overall computing power utilization.

CPO technology can effectively ease the constraints that single-node I/O capability imposes on system expansion and break through the physical limits of copper interconnects.

However, the technology mainly addresses high-speed data transmission at the physical layer. At the protocol layer, complex Scale-Up network topologies and flow-control mechanisms still impose a heavy burden on compute cores.

To build larger Scale-Up networks, compute cores must sacrifice a significant share of chip area and computing resources to handle network tasks.

The emergence of interconnect I/O chiplets fills this critical gap. In high-performance computing chips for AI data center clusters, I/O chiplets serve as the core interface for semantic alignment and protocol carrying.

Drawing on its long-term work in network interconnects and chiplet technologies, Qiyi Moore has already laid out a forward-looking integration path for OSU (Optical Scale-Up) I/O chiplet products and future CPO iterations.

Beyond co-releasing the white paper, Qiyi Moore also brought substantive ecosystem collaboration results to its booth.

For example, it is jointly researching key technologies for next-generation xPU-CPO with TuringQ. The two sides are working across computing power interconnect architecture, resource scheduling optimization, and adaptation to industry scenarios, accelerating the shift of optical interconnects from today’s board-level connections toward higher-integration chip-level fusion, and helping AI data centers use computing power efficiently and deploy services with greater agility.

Together with Singularity Photonics, it is exploring NPO/CPO technologies based on high-speed data interfaces between chiplets, aiming to break bottlenecks in interconnect speed and distance and significantly improve the scale and computing capability of AI data center nodes.

At its booth, Qiyi Moore and Singularity Photonics presented a direct-connect NPO optical interconnect test board. The solution uses Qiyi Moore’s main chip, which internally integrates two independent chiplets simulating a compute chiplet and an I/O chiplet, along with Singularity Photonics’ customized NPO in-package engine.

Qiyi Moore’s systematic layout in optical interconnects is not only an early move to secure a position in next-generation interconnect technology, but also a strategic effort to work with supply-chain partners on the “optoelectronic fusion” evolution path for domestic AI computing power infrastructure.

Domestic Supernode Ecosystem Co-Building Initiative Officially Launched

Supernodes have become the core form of next-generation AI data center infrastructure, and they are also bringing new lessons for the computing power industry.

The basis of competition is expanding from individual chip performance to multi-variable system-level collaboration.

Today, computing power demand from large models is being driven by three exponential curves at once: Scaling Law on the training side, test-time scaling on the inference side, and the surge in call volumes brought by agent applications.

Taken together, these demands are far beyond what single-chip capability improvements can absorb on their own. The factors that increasingly determine the landscape are interconnects, complete systems, software, and system-level coordination.

This is also the key to breaking through in China’s AI data center infrastructure.

Although a number of domestic vendors have launched their own supernode solutions, the broader landscape, while seemingly diverse, carries hidden risks.

Yang Lian, secretary-general of the Shanghai Computing Power Network Association, said at the forum that domestic supernodes still face fragmentation challenges and chokepoint risks in system architecture definition, Scale-Up interconnect protocols, software-hardware collaborative optimization, and cluster RAS capabilities.

Going it alone will not solve the problem. Only open collaboration across the upstream and downstream industrial chain, shared standards, and a common foundation can truly make domestic AI computing clusters usable, performant, and resilient.

Based on this industry consensus, and witnessed by Yang Peijiang, director of the Radio Management Division of the Shanghai Municipal Commission of Economy and Informatization, the Shanghai Computing Power Network Association, Shanghai AI Laboratory, and the East China Branch of the China Academy of Information and Communications Technology formally launched the domestic supernode ecosystem co-building initiative at Qiyi Moore’s AI Networking Frontier Ecosystem Forum.

Major industrial-chain companies including ZTE, Biren Technology, MetaX, Iluvatar CoreX, Enflame, SenseTime, Sugon Information, and Qiyi Moore participated in the initiative.

The launch of the initiative marks an acceleration in forming industry consensus around the domestic supernode ecosystem.

For years, China’s domestic computing power industry has explored a difficult path in fragmented, go-it-alone fashion. This deep collaboration across the entire industrial chain is intended to pool the strengths of all parties, jointly formulate open and compatible supernode interconnect standards, break down technology silos, and push domestic computing power networks toward a substantive step in system-level collaboration, building a solid, independently controllable computing power foundation for the AI industry.

Connecting the Future of AI Computing

In its first appearance at WAIC, Qiyi Moore delivered both a technology and ecosystem statement through a high-level ecosystem forum, three major ceremonial launches, and core exhibits including its fully domestically built full-stack supernode interconnect solution and an OISA protocol-based verification platform for inter-card supernode interconnects.

From initiating the supernode ecosystem initiative to releasing the Co-Packaged Optics (CPO) Technology White Paper; from the first full showing of its domestically built full-stack supernode interconnect solution to the IBGDA joint demonstration based on “domestic GPUs plus domestic RDMA network cards” with partners including Biren Technology,

Qiyi Moore is using a dual engine of technology and ecosystem to deeply integrate into, and actively advance, the development of China’s domestic AI computing power industry.

Looking ahead, as supernode architecture gradually becomes the mainstream form of AI computing power, interconnect technology will rise into the key engine determining system efficiency.

Qiyi Moore will continue to deepen its work in AI interconnect chips and collaborate with more upstream and downstream industrial-chain partners to promote the growth of the domestic supernode ecosystem, contributing core capabilities to the independent control and continued upgrading of China’s AI computing power infrastructure.