On November 11, Huawei's Kirin team released further technical details about the new-generation Da Vinci architecture NPU in the Kirin 9050 series. Three figures stand out: NPU performance is up 140% over the previous generation, power consumption is down 66%, and the chip can run a 30B MoE large model on-device.

Of those three figures, 140% is the easiest to dismiss as marketing. The one that actually carries the most substance is 66%. Phones are not servers — a server can treat electricity as a line-item cost, but a phone cannot. Its computing power budget is locked down by battery capacity and thermal limits. And on-device AI has a peculiar trait: most of the time, it is not answering. It is waiting.

That explains why the document opens not with the model, but with four perception features.

Making Perception Work Without Wake-Up

The four capabilities Huawei announced are: AI Screen Reader, which recognizes and reads aloud on-screen content; XMAGE Smart Shooting 2.0, which uses AI to perceive imaging scenes; AI Eye-Tracking Page Turn, which flips pages by tracking the user's gaze; and Screen-Off Maps 2.0, which handles location-aware map interaction. They process screen content, camera frames, user gaze, and geographic location, respectively.

What these four share is not 'intelligence' — it is 'persistence.' The screen is lit, the camera is framing, the eyes are moving, the person is in motion; all these states need to be read continuously. If every one of them required waking up a large model first, the battery would be drained at step one.

On the hardware side, this maps to the second of three blocks in the new NPU: an ultra-low-power perception engine dedicated to sustained, low-power perception tasks. The other two are a Transformer engine, optimized for the Transformer computation that large models rely on, and the CANN heterogeneous computing architecture, which coordinates different compute resources to improve hardware utilization.

The document also outlines a division of labor: the on-device 'cerebrum' handles user intent comprehension, complex reasoning, and multi-step task planning, while the 'cerebellum' manages always-on, low-power perception and fast response. In chip terms, this maps to two fundamentally different operating states — one that bursts at high power for short intervals, and one that holds the line at ultra-low power over long stretches. Putting both in one chip is, in essence, answering the question of 'who is on duty while the phone is idle.'

How 30 Billion Parameters Fit in a Phone: Use Only 2 Billion at a Time

30B refers to a model with 30 billion total parameters. MoE, or Mixture of Experts, contains multiple expert modules internally and activates only a subset of them per task, rather than engaging all parameters at once. Huawei's figures: this 30B model has 30 billion total parameters, roughly 2 billion activated parameters per inference, and less than 2.5GB of incremental memory usage.

The 2 billion figure is worth pausing on. By Huawei's own numbers, the parameters actually involved in each inference run amount to roughly one-fifteenth of the total — 2 divided by 300 equals about 6.7%. The model's capability ceiling is set by the 30 billion side; the cost of a single inference is set by the 2 billion side. Those two things have been decoupled. Every MoE does this kind of split, but only at this ratio does it become feasible to fit one inside a phone.

The 2.5GB figure deserves an even longer pause. Even stored at 4-bit precision, 30 billion parameters would require somewhere in the teens of gigabytes — by arithmetic alone, 2.5GB cannot be the full model's memory footprint. It is more likely the 'incremental' portion: the bulk of the model does not reside permanently in memory but is tiered. Frequently used parts stay in RAM; the rest are stored elsewhere and pulled in on demand. The document describes the technique as low-bit quantization combined with multi-level storage-compute co-optimization, and the phrase 'multi-level' lines up exactly with this approach.

This approach is a fundamentally different thing from 'making the model smaller.' Making it smaller trades capability for size. Multi-level storage-compute trades scheduling complexity for size while keeping capability intact. The cost of the latter is hidden inside the system: what goes on which tier, when to prefetch, and how to roll back if a prefetch misses — none of that shows up on a spec sheet, but it determines how long the user waits after pressing a button.

More Than One Model: A Whole Roster on Device

The Kirin 9050 series supports more than just the 30B model on-device. There is also a 6B image editing model, a 7B Dense text model, and a small multimodal perception model, handling image processing, text tasks, and scene perception, respectively. Models of different sizes divide the work, and the phone dispatches whichever one fits the task.

The word Dense here is a deliberate contrast. The 30B is MoE; the 7B is Dense — a dense model has every layer fully engaged in computation, with no expert routing step. Having both architectures coexist suggests that model selection is task-driven: MoE when you need to compress per-inference cost, Dense when you need predictable latency.

What this arrangement means for the user, the document states plainly: certain tasks can be completed directly on the phone without connecting to the cloud each time. The use cases Huawei highlights are complex task planning, intelligent photo editing, and multimodal perception — all categories where the input is local, privacy-sensitive, and cannot afford to wait.

Logic Folding: Change the Packaging, Not the Process Node

Everything above concerns the compute units. The final section of the document lands on the overall chip design: logic folding.

At its core, it is a 3D approach to chip co-design — treating multiple dies as a single complete chip and rearranging the layout of logic circuits. Logic that was previously laid out flat can be folded into stacked upper and lower layers, then connected via hybrid bonding to achieve high-density vertical interconnects. This shortens signal paths and increases the chip's internal integration density and coordination efficiency.

Hybrid bonding is the linchpin of this technology, enabling signal communication between different logic layers through high-density connections. Huawei's numbers: the Kirin 9050 series has over 50 million hybrid bonds, more than 5 million effective signal interconnects, and a 53.5% increase in transistor density. The Kirin 9050 Pro has a hybrid bonding pitch of 1.5 micrometers.

Fifty million bonding points and 5 million effective signal interconnects — the two figures differ by an order of magnitude. The significance of hybrid bonding is not just density but distance. Vertical interconnects compress what would otherwise be a long, flat routing path tracing out to the chip's edge into a short vertical jump between two stacked layers. The shorter the signal travels, the lower the latency and power draw — which is why hybrid bonding delivers gains in both density and energy efficiency at the same time.

String the three threads together: the NPU determines how much can be computed per unit of time, logic folding determines how far data has to travel inside the chip, and the on-device model architecture determines how much computation a single task requires. Multiply all three together, and you get the outcome: 'more AI tasks can be completed locally.' That is also how the document closes.

The Three Figures Are One Chain

Back to those three opening numbers. Performance up 140%, power down 66%, 30B on-device — they are not three independent report cards. They are three links in a single chain: folding pushes density and interconnects higher, giving the NPU room to house the Transformer engine and perception engine; energy efficiency improves enough that always-on perception can stay running; and the model architecture compresses activated parameters to 2 billion and incremental memory to 2.5GB, making it possible to fit 30 billion parameters inside a phone.

Each link constrains the next. This is also why upgrades of this kind are hard to pull off with a single-point breakthrough: make only the NPU stronger and the model will not fit; make only the model smaller and capability suffers; make only the packaging better and there are no matching compute units to use that bandwidth.

One parting note: the yardstick has shifted. The old marketing line for on-device AI was 'can it run?' — getting a 7B model to run was considered a generational leap. Now the question has become 'how big can it run?' and 'how much power does it cost to keep running?' The latter is harder to fudge. Parameter counts can go on a slide deck; power consumption has to be paid out in battery life.