The ninth China International Import Expo will be held in Shanghai from November 5 to 10. The China Pavilion at the national exhibition, themed “Opening Up New Horizons, Building a Shared Future,” is centered on the blueprint for China’s 15th Five-Year Plan. MetaX (688802.SH), the only Chinese GPU company selected for this year’s pavilion, is bringing two products: the XiJing S600 supernode and a heterogeneous dual-engine computing power rack jointly developed with Dongfang Suanxin.

The two products address different questions. The first asks how many cards can fit into a rack and whether they can communicate without waiting. The second asks whether two chips can be used when no single chip can excel at two different workloads at once.

MetaX offered its own assessment in the press release: competition in computing power is shifting from peak single-card performance to system efficiency, and whoever can “produce” tokens at lower cost and higher efficiency will gain the upper hand in commercializing AI. That is the company’s framing, but it does capture the design rationale behind both systems.

A 128-Card Rack With No Switching Oversubscription

The XiJing S600 is a system-level product designed for large-model training and inference and for building AI data centers. It uses MetaX’s domestically developed flagship XiYun C600 GPU, along with the company’s MXMACA software stack and MetaXLink high-speed interconnect.

The key specification is that a single rack supports full switching across 128 cards with no bandwidth convergence.

That claim needs unpacking. Communication between GPUs relies on switches to route traffic. Conventional racks use multilayer switching and oversubscription: because switches have a limited number of ports, each card cannot have a dedicated path to every other card. Bandwidth is therefore allocated proportionally, forcing cards to queue and share capacity when they communicate simultaneously. The industry calls this the convergence ratio. A ratio below one means effective bandwidth falls short of the theoretical maximum.

That is manageable with a small number of cards. But large-model training uses tensor parallelism and expert parallelism, and communication traffic rises with the card count. The more cards in the system, the more pronounced the delays caused by convergence become. Doubling the number of cards does not necessarily double computing power, because the additional cards may spend much of their time waiting for data.

“Full switching across 128 cards with no bandwidth convergence” means communication between any two cards inside the rack runs without a bandwidth penalty. In effect, the rack becomes one large, integrated compute unit rather than a collection of independent servers. Scale-out expansion can then extend the architecture to clusters with tens of thousands of cards.

That is the practical meaning of a supernode. It is not simply a larger server; it integrates switching into the rack so that internal communication functions like direct chip-to-chip connectivity.

The ‘Three Zeros’ Eliminate Tens of Thousands of On-Site Cables

MetaX calls its engineering design a high-density orthogonal full-rack “three-zero” architecture: zero cables within compute nodes, zero cables within switching nodes, and zero cables between compute and switching nodes.

Cabling is an underestimated issue in data centers. A standard rack can easily contain more than 1,000 network, fiber-optic and power cables, while a cluster with tens of thousands of cards can require hundreds of thousands. Every cable must be plugged in manually, creating another opportunity for an incorrect connection, a loose plug or an inadequate bend radius. Cable bundles can also obstruct airflow and impair cooling.

The cable-free design uses orthogonal connectors to plug compute nodes directly into switching nodes, with the backplane providing the electrical connection. Assembly shifts from wiring components according to a diagram to simply sliding boards into place, while the data center no longer needs its cable trays reconfigured. That is what the press release means when it says the system can be deployed quickly without modifying the facility.

Combined with a decoupled, modular architecture, the system’s value lies less in the amount of copper it saves than in reducing variability in deployment and operations. In large clusters, the hardest failures to diagnose often come not from a broken chip but from a loose cable.

MoE Inference Combines Two Fundamentally Different Workloads

The heterogeneous dual-engine rack provides the other half of the answer, and it is the more notable part of this launch.

Understanding it requires a look at what happens during mixture-of-experts, or MoE, inference. An MoE model does not invoke all its parameters for every inference request. Instead, a router activates only a subset of experts. This allows the model to scale up its parameter count while keeping the computation required for each inference under control. The tradeoff is that inference is split into two stages with fundamentally different characteristics.

One stage is attention computation, which primarily consists of large-scale matrix multiplication. It demands floating-point computing power, an area where GPUs excel. The other is the expert network, where the challenge is moving data rather than performing calculations. Tokens must first be routed to the appropriate experts, while expert weights are distributed across GPU memory. Much of the time is spent retrieving data from memory, making memory bandwidth, rather than computing power, the bottleneck.

The two workloads have different bottlenecks: one is constrained by FLOPS, the other by bandwidth. Running both on the same type of chip inevitably leaves some resources idle. A chip optimized for computing power wastes compute cycles on expert layers, while a high-bandwidth chip cannot fully use that bandwidth when running attention workloads.

AE Separation: Dedicated Chips for Attention and Experts

MetaX and Dongfang Suanxin call their approach AE separation, with A standing for Attention and E for Expert. The two stages are physically decoupled and assigned to chips with different characteristics, an arrangement the press release describes as “dual-chip specialization.”

The division of labor works as follows: MetaX’s XiYun C600 primarily handles compute-intensive tasks such as contextual correlation, while Dongfang Suanxin’s DF1000 primarily handles memory-intensive tasks such as sparse activation. Each chip plays to its strengths, allowing the system, in the company’s words, to “break through both the memory wall and the compute wall.”

This is a different approach from simply making one task run faster. The latter pushes farther along a single axis; the former acknowledges that the axis has reached its limit and shifts to another one.

Separation comes at a cost, however. The output from the attention stage must be sent to the expert layer and then returned after expert computation. The overhead of moving tokens back and forth between the two chips must be lower than the idle capacity the architecture eliminates. Whether the approach works therefore depends on whether the data path between the chips is wide and fast enough. The press release provides no figures for that layer, saying only that the system is designed for cloud inference.

Two Chips Working Together on Speculative Decoding

The press release outlines a second use for the same hardware: speculative decoding.

The principle behind speculative decoding is straightforward. A small, fast model first predicts the next several tokens and produces a draft sequence. A larger model then verifies the entire sequence in one pass, retaining correct tokens and restarting from the first incorrect one. When the acceptance rate is high enough, the process can substantially improve overall speed.

Here again, the two stages have different characteristics. Draft generation is serial, producing one token at a time, and requires extremely low latency. Verification is batched, processing an entire sequence at once, and depends on parallel throughput. In this heterogeneous system, the DF1000 generates draft candidates as a low-latency stream, while the C600 performs rigorous verification in batches. The press release calls this “two chips working as one.”

The same pair of chips is divided by compute-intensive versus memory-intensive work in MoE inference, and by latency-sensitive versus throughput-sensitive work in speculative decoding. The logic behind the two divisions differs, but both point to the same premise: no single chip can be optimal across every dimension.

From Peak Single-Card Performance to System Efficiency

That brings us back to the assessment at the beginning.

Peak single-card performance is a theoretical measure of how many floating-point operations a chip can execute under ideal conditions. In real model workloads, however, cards must communicate with one another, data must move from GPU memory to compute units, batch sizes are constrained by memory capacity, and workloads fluctuate over time. Once these costs are added together, actual throughput is often only a fraction of the theoretical peak.

“System efficiency,” then, measures not how powerful one chip is, but how much of a system’s theoretical computing power can be put to work on real workloads. Non-blocking communication across 128 cards prevents cards from queuing for bandwidth; the “three-zero” design reduces deployment and operational failures; and AE separation avoids forcing dissimilar workloads onto the same hardware. All three serve the same objective.

Using tokens as the unit of measurement takes this logic to its conclusion: instead of looking at a card’s rated performance, measure how many usable tokens can be produced per kilowatt-hour of electricity. That metric is more practical for buyers and harsher on vendors because it factors interconnects, the software stack and deployment efficiency into the denominator.

The press release concludes by calling for chips, models, inference frameworks and cloud platforms to be jointly optimized around a common objective. Framed as an appeal for industry collaboration, the statement also identifies the real barrier to this approach: the value of heterogeneous computing does not come from installing two chips in the same rack, but from whether the software layer can shield model developers from having to care which chip is performing the computation.