After DeepSeek V3.1 was released, one official comment set China’s AI community buzzing:

“New architecture” and “next-generation domestic chips” amounted to fewer than 20 Chinese characters, but the message carried a huge amount of information.

Shares of domestic chip companies rose in response. Cambricon, for example, jumped nearly 14% in intraday morning trading today, making it the most valuable company on the STAR Market by market capitalization.

Semiconductor ETFs also surged 5.89% in just half a day. (No idea whether High-Flyer Quant, the company behind DeepSeek and the source of the news, took the chance to trade the move .)

So what exactly is UE8M0 FP8? And what does “next-generation domestic chip” refer to?

The questions came one after another, crowding people’s minds.

On Zhihu, plenty of experts also began explaining the basics while offering their own take on what had happened.

With a learning mindset, let’s start with the concept of UE8M0 FP8.

What Is UE8M0 FP8?

The term “UE8M0 FP8” can be split into two parts. UE8M0, the first part, is the “scaling factor” in the MXFP8 path.

MXFP8 is an 8-bit microscaling block format defined in the Microscaling (MX) Formats Specification v1.0 released by the Open Compute Project in 2023.

The Open Compute Project is an open-source hardware collaboration initiative launched in 2011 by Facebook, now Meta, together with Intel, Rackspace and others. Its goal is to improve industry efficiency by sharing data center and server designs.

Its membership is formidable: overseas participants include Microsoft, Google, Amazon, AMD and NVIDIA, while Alibaba, Tencent and Baidu are among the Chinese companies involved.

Back to MXFP8. It is built on FP8, an encoding method that compresses conventional floating-point formats into 8 bits.

The core idea of MXFP8 is to first split a tensor into fixed-length “blocks,” then assign each block its own integer power of two as a “scaling factor.” All values in the block are divided by that factor before being written as FP8.

This block-level scaling, rather than whole-tensor scaling, lets MXFP8 preserve an 8-bit width while expanding the usable dynamic range by dozens of times.

The “scaling factor” here also consists of 8 bits, including sign, exponent and mantissa fields. Developers can decide how to allocate those 8 bits among the three fields.

The sign field only distinguishes whether a sign exists. If present, it takes one bit; if absent, it takes none. The U in UE8M0 means unsigned. A signed version can be written as S or omitted.

E and M indicate how many bits are allocated to the exponent and mantissa fields, respectively. E8M0 means all 8 bits are assigned to the exponent field.

Other common formats include E4M3 and E5M2, which are also often used for the data body outside the scaling factor. Both include a sign bit, with the remaining 7 bits allocated between exponent and mantissa.

DeepGEMM, DeepSeek’s previously open-sourced FP8 GEMM kernel project with 5.6k stars, already supports UE8M0, though the project mainly targets NVIDIA chips and the CUDA ecosystem.

So what is the benefit of using an all-exponent representation for the scaling factor?

First, because UE8M0 has no mantissa or sign bit, when a processor reconstructs data using the scaling factor, it only needs to multiply by the corresponding power of two, effectively shifting the exponent. It does not need floating-point multiplication, normalization or rounding logic, shortening the critical clock path.

UE8M0 also covers a dynamic range from 2^(-127) to 2^128, and its exponent table can easily accommodate that span, leaving ample room for later block scaling.

UE8M0 can also address the problem that single-scale FP8 cannot handle large and small values at the same time, causing overflow or compression to zero. When UE8M0 is used as the block scale, the error-rate curve drops from a full curve to a much lower horizontal line, sharply reducing information loss while maintaining 8-bit tensor precision.

Now that we understand the benefits of UE8M0 FP8, we can explain why it is a better fit for “next-generation domestic chips.”

Most mass-produced domestic AI accelerators still use FP16/BF16 plus INT8 compute paths and have not integrated full FP8 multiply-add units such as E4M3 or E5M2.

However, newer domestic chips scheduled for first release in the second half of 2025, such as Moore Threads’ MUSA 3.1 GPU and VeriSilicon’s VIP9000 NPU, have already listed support for “native FP8” or “Block FP8” in marketing materials, and have jointly validated the UE8M0 format with 15 companies including DeepSeek and Huawei.

Although next-generation domestic chips are already preparing for FP8, HBM/LPDDR bandwidth still lags significantly behind top-tier chips.

UE8M0 adds only an 8-bit scaling factor to a group of 32 FP8 values. Compared with traditional 4-byte, or 32-bit, FP32 scaling, it directly saves 75% of traffic. This kind of space-saving measure is seen as an important optimization direction for next-generation architectures.

Which Domestic Chip Did DeepSeek Optimize For?

After figuring out what UE8M0 FP8 is, users came back to the next question:

Which domestic chip company is DeepSeek talking about?

With the official account deliberately keeping people guessing, attention first turned to the eight vendors in the first batch to pass “DeepSeek large model adaptation.”

Among them, the “top seed” favored by many is Cambricon. The market reaction was direct:

As of 10:25 today, Cambricon had jumped nearly 14% intraday, with a market capitalization above 494 billion yuan, surpassing SMIC to become the largest company on the STAR Market by market value (subject to the latest actual figures).

The reason is straightforward: the company’s MLU370-S4, Siyuan 590 and latest 690-series chips all support FP8 computing, and it has long been relatively advanced in architectural design and low-precision compute optimization.

For similar reasons, Hygon, MetaX, Zhonghao Xinying and even Moore Threads, which is not on the list, were all named by users one by one:

Hygon: Its Deep Computing No. 3 DCU supports FP8 computing and has room for further optimization;

MetaX: The Xiyun C600, released in July this year, also supports FP8-precision computing;

Zhonghao Xinying: Its “Shana” TPU AI chip supports FP8 precision;

Moore Threads: As one of the few Chinese GPU vendors with native FP8 support, its flagship MTT S5000 supports FP8-precision computing.

At the same time, some vendors that are highly likely to “get on board with FP8” soon also appeared across the various roundups.

Huawei Ascend, for example, does not yet support native FP8 on the Ascend 910B or 910C, but the official roadmap already specifies “native FP8 in Q4 2025.” Many therefore expect the 910D, possibly its name when launched in 2026, to be the so-called “next-generation chip.”

Beyond these companies, a long list of chipmakers appeared in the discussion, making for an unusually lively scene.

Although all the speculation has yet to produce a final answer, that did not stop the market from responding enthusiastically. According to the latest reports, domestic chip-related stocks opened broadly higher today, the STAR 50 rose 3% to a nearly three-and-a-half-year high, and the chip supply chain strengthened as a group.

So why is everyone celebrating? What would it actually mean if these domestic chips support UE8M0 FP8?

Combining the current views from China and abroad, it can all be summed up in one sentence:

It signals that China’s domestic AI ecosystem is moving into a stage of software-hardware co-design, which could materially reduce reliance on foreign computing power from NVIDIA, AMD and others.

The logic is simple and clear. Because the UE8M0 FP8 precision format has the advantages described above, including lower bandwidth, lower power consumption and higher throughput, the same hardware can run larger models in the future, substantially improving the “cost-performance ratio” of domestic chips.

In other words, these domestic chip vendors will be more competitive, which is why the news is seen as positive.

Viewed from another angle, by changing the precision format, DeepSeek is effectively aligning itself with the performance sweet spot of domestic chips. This software-hardware co-design model undoubtedly pulls domestic chip companies into a shared ecosystem coordinate system.

It resembles the old “Wintel alliance”: Microsoft and Intel built an ecosystem moat in personal computing through deep technical coupling, except this time the players are DeepSeek and domestic chip vendors.

One More Thing

In fact, the official text mentioned UE8M0 FP8 in only one sentence:

It should be noted that DeepSeek-V3.1 uses UE8M0 FP8 Scale parameter precision.

And it was placed in a fairly “hidden” spot, tucked after a long, detailed introduction to feature updates.

If the official account had not added a comment in the comment section, most people probably would not have felt much.

So whether the move was accidental or deliberate is hard to say. Either way, it was quite subtle .