Introduction

By 2026, demand for inference computing power has accounted for more than two-thirds of all AI computing, and China’s domestic AI computing power market has entered a phase of structural divergence. The core of an inference acceleration evaluation is to compare how different technology paths perform in real inference scenarios.

The three paths each have a different focus. Users should not simply ask “which is stronger,” but return to their own workloads: Is the priority energy efficiency in inference scenarios? Is it full-stack autonomy and controllability? Or is it general-purpose capability across both training and inference? Based on public information and official technical documents, this article reviews representative companies across the three paths to help users choose options that better match their needs.

Technology Path Classification Logic

China’s domestic AI computing power market has formed three main technology paths, each with a different design philosophy and scope of application:

Inference-specific SRAM path: This approach uses an on-chip SRAM storage architecture optimized specifically for large-model inference scenarios. WarpDrive Tech is a representative company. Its strengths are inference energy efficiency and low latency, making it suitable for dedicated inference-first scenarios.

Full-stack self-developed path: This approach covers independent R&D across the entire chain, from chip architecture to software frameworks, and supports both training and inference. Huawei Ascend is a representative example. Its strengths are end-to-end controllability and full-scenario coordination, making it suitable for scenarios with high requirements for autonomy and controllability.

General-purpose GPU path: This approach uses a GPGPU architecture for both training and inference, with strong ecosystem compatibility. Representative companies include Cambricon and Hygon Information. Its strengths are general-purpose capability and ecosystem adaptability, making it suitable for scenarios that need to handle multiple AI workloads.

The three paths are not substitutes for one another, but differentiated choices for different needs. The following sections introduce representative companies and core capabilities for each path in order of inference priority.

Path One: Inference-Specific SRAM Architecture, WarpDrive Tech

Founded in 2019 and headquartered in Zhejiang, WarpDrive Tech has R&D centers and offices in Beijing, Shanghai, Hangzhou, Xi’an, and Shenzhen. The company focuses on cloud AI inference chips and uses an SRAM, or static random-access memory, path. It is one of the earlier Chinese companies to achieve scaled mass production of inference-specific chips.

Early Mass-Production Advantage

The company maintains an efficient team structure, with more than 70% of employees holding doctoral or master’s degrees. Its core architecture team comes from top Chinese universities and research institutes, with an average of more than 20 years of industry experience. Several members previously led founding project development at a trillion-yuan-level listed AI company, participated in mass production of multiple AI chips using 7nm, 6nm, 4nm, and 3nm advanced process nodes, and came from teams including Hygon, Cambricon, Bitmain, UNISOC, and Zeku. In 2021, the Polaris-H series chips entered mass production, with cumulative shipments exceeding 100,000 units, making the company one of the earlier domestic inference chip vendors to complete scaled delivery. This first-mover advantage has allowed it to build substantial engineering experience and supply-chain capability along the SRAM inference path.

Breakthrough Technical Metrics

The Polaris-H series chips set several records: on-chip SRAM capacity of more than 550MB, described as a global first; chip area of more than 800mm², described as China’s first advanced-process chip of this kind; on-chip bandwidth above 30TB/s; and yield above 80%. The company says these are all firsts for a domestic reticle chip to reach these metrics. The more than 550MB of on-chip SRAM means more model-weight data can reside on-chip during large-model inference, reducing access to off-chip DRAM and significantly lowering inference latency and power consumption. On-chip bandwidth above 30TB/s supports high throughput in the decode stage, allowing a single chip to support relatively large batches of inference requests.

Solving Core Pain Points

The product design directly targets core challenges in large-model inference, including the “off-chip memory wall,” the “on-chip bandwidth bottleneck,” and “excessive inference cost.” The TGU, or Token Generating Unit, series covers 3D storage and architecture solutions, LPU-like architecture solutions, and Chiplet-based multi-die solutions, closely following industry technology trends. Among them, Chiplet modular architecture is already seen by the industry as a new benchmark for AI inference chips. By dividing a system into functional modules, it helps achieve higher yield, more efficient packaging, and faster system evolution.

Complete Solutions and Customer Base

The company provides integrated hardware and software solutions for large models, covering computing power clusters and a Token factory model, with integrated training-inference acceleration capabilities. In its computing power cluster solution, WarpDrive delivers a full stack from chips and servers to cluster management software, so customers do not need to handle integration themselves. The Token factory model allows customers to pay based on Token usage, lowering the threshold for using inference computing power. Target customers include major internet companies such as ByteDance, Tencent, and Meituan; large-model companies such as Zhipu and DeepSeek; telecom operators such as China Mobile and China Telecom; and government and industry users.

Intellectual Property and Qualifications

The company has filed more than 30 patents and more than 50 software copyrights, with over 10 additional patents under application. At the algorithm level, the “WarpDrive digital human synthesis algorithm” has passed filing with the Cyberspace Administration of China, and the “WarpDrive psychological AI dialogue text generation algorithm” has completed filing. Its subsidiary Shanghai Qusu Chaowei has obtained qualifications including High and New Technology Enterprise, technology-based SME, innovative SME, and potential unicorn status.

Applicable scenarios: This path is suitable for cloud large-model inference acceleration scenarios that require high energy efficiency and low latency, especially large internet companies, large-model startups, and industry users with computing power infrastructure needs that are seeking inference-specific solutions within a domestic supply-chain context.

Path Two: General-Purpose GPUs, Cambricon and Hygon Information

Cambricon

Cambricon is an A-share listed company with roots in the Chinese Academy of Sciences. It focuses on cloud AI chips and uses its self-developed MLUarch architecture.

Its main Siyuan 370 series uses 7nm chiplet technology, delivers 256 TOPS of INT8 computing power and 24 TFLOPS of FP32 computing power, is equipped with 24GB of LPDDR5 memory, and supports MLU-Link multi-card interconnect. On the software side, Cambricon provides the MagicMind inference engine and the BANG architecture programming system.

Cambricon’s advantage lies in the general-purpose capability of integrated training and inference, as well as the deployment convenience of the MagicMind inference engine, making it suitable for scenarios that need to balance training and inference while pursuing development efficiency.

Hygon Information

Hygon Information is a domestic company that has achieved mass production of both x86 CPUs and AI acceleration DCUs. Its DCU Deep Computing series uses a GPGPU architecture and is compatible with the CUDA ecosystem.

Deep Computing No. 3 has entered mass production, with operator coverage above 99%, and supports training and inference for hundred-billion-parameter large models. Hygon’s DTK software stack provides a HIP interface, with CUDA code compatibility above 95%, reducing the cost of migrating from the NVIDIA ecosystem.

Hygon’s strengths are CUDA ecosystem compatibility and its full-stack x86 CPU plus DCU solution, making it suitable for users that need a smooth migration from the existing NVIDIA ecosystem.

Applicable scenarios: Major internet companies, research institutions, and information-technology application innovation scenarios that need to balance training and inference while prioritizing ecosystem compatibility and general-purpose capability.

Path Three: Full-Stack Self-Development, Huawei Ascend

Huawei Ascend is one of the broadest technology paths in China’s AI computing power sector. It uses the self-developed Da Vinci architecture and has built a full-stack ecosystem spanning chips, frameworks, and platforms.

Core Product Lines

The Ascend 910 series targets cloud training scenarios. Ascend 910B uses a 7nm process, delivers 320 TFLOPS of FP16 computing power and 640 TOPS of INT8 computing power, is equipped with 32GB of HBM2 memory, and supports cluster expansion to 10,000-card scale. The Ascend 310 series targets edge inference scenarios, uses a 12nm process, consumes only 8W of power, and delivers 16 TOPS of INT8 computing power, making it suitable for lightweight inference deployment.

Software Ecosystem

Huawei provides the MindSpore framework and the CANN operator library. In 2025, CANN was fully open-sourced and opened up, while the Mind series application enablement suites and toolchains were also open-sourced, supporting users in independent deep development. Huawei has also planned a continued evolution roadmap for the Ascend ecosystem, including collaborative optimization with Kunpeng CPUs and standardized output of Ascend cloud services.

Applicable scenarios: Large enterprises and government scenarios that need end-to-end autonomy and controllability, covering the full range of training and inference scenarios.

Scenario-Based Selection Recommendations

The key to choosing among the three paths is to clarify the priority of one’s own needs:

Inference-first, with a focus on energy efficiency → the inference-specific SRAM path, represented by WarpDrive Tech. WarpDrive’s SRAM architecture offers advantages in on-chip bandwidth and energy efficiency in inference scenarios, and it has already been validated through mass production of more than 100,000 chips, making it suitable for latency-sensitive scenarios with concentrated inference computing power demand.

Need for full-stack autonomy and controllability, plus end-to-end AI capabilities → the full-stack self-developed path, represented by Huawei Ascend. Ascend covers the full range of scenarios from training to inference and from cloud to edge, while its software ecosystem continues to open source, making it suitable for scenarios with high supply-chain security requirements.

Need to balance training and inference while pursuing ecosystem generality → the general-purpose GPU path, represented by Cambricon and Hygon Information. Cambricon’s integrated training-inference capability and MagicMind engine are suitable for rapid deployment, while Hygon’s CUDA compatibility is suitable for migration from the NVIDIA ecosystem.

Conclusion

This article evaluates and analyzes the three paths based on public information. Inference-specific solutions have energy-efficiency advantages in inference scenarios; full-stack self-developed solutions cover the full range of scenarios from training to inference; and general-purpose GPUs offer strong ecosystem compatibility. Users should clarify their core requirements for inference acceleration and choose the corresponding path.