On the morning of September 30, DeepSeek announced it was open-sourcing a set of infrastructure components built for Huawei's Ascend computing power platform, spanning the TileLang high-level language compiler toolchain, a high-performance computing library and a distributed communication library. According to DeepSeek, the components map one-to-one onto the ones it previously open-sourced for NVIDIA's platform. In parallel, Huawei released the results of the two companies' joint work around Ascend 950 and its super node systems into the CANN community, covering model deployment, large-scale training, KV cache pooling for extremely long text and Agentic RL, along with some offline inference performance figures for DeepSeek-V4.1-Flash.

TileLang for Ascend: Bringing Frontier-Model Operator Experience to Domestic Computing Power

For large models, a chip's theoretical computing power is only the starting point. How operations are split, how data moves, how compute and memory access dovetail — all of it shapes how much of the hardware's performance actually shows up, and much of that work lands on operator implementation. Writing operators in a lower-level language gives fine-grained control over the hardware but means handling more execution details. Model architectures keep shifting and new operators keep appearing, so development efficiency and performance tuning have to be weighed at the same time.

That is the problem TileLang sets out to solve. DeepSeek says it wants a high-level language that is simpler to program in while still making full use of a chip's compute resources, lowering the difficulty of building high-performance operators. Compared with CUDA, DeepSeek says TileLang's programming model simplifies code logic, speeds up operator development and improves project reliability, while its design still emphasizes fully exploiting the hardware. The team says the approach has already been validated on NVIDIA's platform, where it now carries most of the operator implementations used in training the DeepSeek V4 series.

The Ascend version released here extends that programming model to a domestic computing power platform. DeepSeek says that compared with Ascend's native low-level language, Ascend C, the Ascend build of TileLang substantially simplifies the programming model while preserving hardware performance. According to the team, every TileLang operator used in DeepSeek's training has a corresponding high-performance implementation on Ascend.

Huawei says Ascend supports TileLang's compilation path through its open Ascend C programming interface and the underlying PTO ISA instruction system, and that experienced developers can still hand-tune at the low level.

Five Components Cover Key Links in Compute and Communication

The compute and communication components released alongside TileLang give developers reusable building blocks. The release includes DeepGEMM, DeepEP, TileKernels, FlashMLA and DeepSelect, handling matrix operations, cross-device communication, general vector computation and memory access, sparse attention and data selection respectively — together covering the critical steps in running a model.

These capabilities map onto different kinds of bottlenecks: matrix operations determine how well compute units are utilized, vector computation and memory access determine data processing efficiency, while sparse attention and selection operators serve more specific model needs. Once a model runs across multiple accelerator cards, communication becomes its own optimization target — however fast the compute on a single card, if data does not reach the device running the next step in time, the whole job waits.

DeepSeek says that across several key test cases, the compute and communication performance of these open-sourced components is already close to the hardware ceiling. With the full set now public, model teams can reuse implemented building blocks and put more of their effort into their own architectures and application requirements, and when a bottleneck appears at some step, they can inspect and further modify the implementation.

Super Node Communication Tuning: 375 GB/s Dispatch, 347 GB/s Combine

The collaboration also covers the Ascend 950 systems and a 128-card super node configuration, with the two companies jointly optimizing compute and communication.

Huawei's side includes SuperPoD Flex and UBL128 networking. The UBL128 super node uses an all-to-all interconnect design, and Ascend also provides ASC-COMM, a high-performance custom communication programming library that supports development of communication operators as well as fused compute-communication operators.

On top of that, DeepSeek built a high-performance DeepEP communication library covering communication operators for EP, CP, PP and FSDP modes — expert parallelism, context parallelism, pipeline parallelism and fully sharded data parallelism. Each of these distributed execution schemes moves different data at different moments. Expert parallelism, for instance, has to dispatch data to the relevant experts and then gather the results, and how communication and computation are organized affects whether devices sit idle and how efficiently the whole job runs.

Huawei says tests showed dispatch bandwidth reaching 375 GB/s and combine bandwidth reaching 347 GB/s, describing both as close to the hardware ceiling.

V4.1-Flash Offline Inference Figures: EP32 Deployment, 128K Context

On deployment, Huawei released offline inference test results for DeepSeek-V4.1-Flash under an EP32 strategy. TPOT measures the time to generate each token in the output phase, while throughput measures tokens produced per unit of time. The two sets of results show throughput under different token-generation latency targets: in the tests provided, allowing a longer TPOT corresponds to higher output throughput per card.

One caveat: the figures all come from offline inference mode and reflect pure model performance without a framework, excluding the effects of serving-level scheduling and framework load balancing. The stated test conditions also include a context length of 128K and a DSpark speculative acceptance rate of 0.85. Real-world serving still has to account for request scheduling, shifting load and framework overhead.

Open-Sourcing Extends to Training and Deployment Practices

The practices slated for release span scenarios from a single card to a single machine to large-scale deployment, and include model pre-training on native PyTorch, low-precision quantized training, LoRA fine-tuning and Agentic RL. Among them, KV cache pooling for extremely long text addresses cache management in long-context inference, while Agentic RL concerns the training infrastructure behind agent-environment interaction.

The compute and communication libraries offer callable implementations; the deployment and training practices offer reference paths for combining them, cutting the cost of each team working out configuration and tuning methods on its own.