On October 23, Suzhou-based AI high-performance chip company Yizhu Technology announced it had closed a financing round of more than 1 billion yuan, with proceeds earmarked for further R&D, product iteration and commercialization.

Founded in June 2020 and operational since 2022, Yizhu is headquartered in Suzhou with subsidiaries in Shanghai, Hangzhou, Chengdu and Changsha. The company says it has built its technology around 3D DRAM and pioneered a fully digital, general-purpose compute-in-memory architecture, with a product lineup spanning accelerator cards, workstations, all-in-one systems and inference clusters. It also offers its in-house YICA software platform, compatible with mainstream ecosystems including CUDA and PyTorch, positioning its high-throughput, cost-efficient and low-power computing power offerings at data centers and AI cloud computing.

Founder, chairman and CEO Xiong Dapeng holds a PhD in semiconductors from the University of Texas at Austin. He taught at Huazhong University of Science and Technology before joining ADC Telecommunications as a senior technical manager and later a major product line manager. He also served as China general manager at US AI chip firm Wave Computing, running its China business, and brings nearly 30 years of chip R&D, product, marketing and management experience across China and the US. Core members of the engineering team average more than 25 years in high-end IC design and volume production, with capabilities spanning process and devices, architecture, circuit design and the software stack.

Yizhu has raised multiple rounds since its founding. In October 2024, it announced a round in the hundreds of millions of yuan led by overseas fund Prosperity7 Ventures, with participation from Shenzhen Shengshi Technology and Xingzhi Capital, among others. In October 2025, it closed a new round joined by Xingxiang Capital, ABC International, Yingke Zhide and Heding Gongzi Capital.

Investors in the latest round were not disclosed.

From ReRAM to 3D DRAM: The Trade Is for Capacity

Yizhu has staked out a "general-purpose compute-in-memory plus super-heterogeneous" approach, organizing its core technology around 3D DRAM-based compute-in-memory, and has published what it calls the three laws of general-purpose compute-in-memory.

Its rationale for compute-in-memory is straightforward: under the von Neumann architecture, data must shuttle repeatedly between memory and compute units, creating three bottlenecks — the memory wall, the power wall and the compilation wall. Compute-in-memory moves computation inside the memory array, eliminating data movement costs at the architectural level. The company claims this delivers an energy-efficiency gain of more than 8 to 10 times over mainstream PCIe boards.

The more telling shift is in the memory medium. Yizhu did not start with 3D DRAM: the memory medium in its compute-in-memory chips moved from ReRAM to 3D DRAM, a choice the team attributes to greater capacity, mature technology, better stability and lower cost.

Put another way, the switch was less about speed than about capacity — and capacity directly determines how large a model a single chip can hold.

Taped Out, but the Scorecard Comes From Simulation

On product progress, Yizhu says its fully digital, general-purpose compute-in-memory AI chip based on 3D DRAM has completed tape-out, with full-chain validation from theoretical architecture through to silicon, and that test results for the commercial chip largely met preset design targets.

Three things need to be kept separate here: tape-out completed, tests passed, and volume production shipping. The company has cleared the first two. The third has not happened yet.

On performance, the company says that compared with mainstream cloud GPUs, its general-purpose compute-in-memory approach delivers several times the performance at roughly one-fifth the power and one-sixth the cost, cutting total cost of ownership for large-model inference compute by as much as roughly one-sixth.

The figures benchmarked against NVIDIA's H200, meanwhile, come from an FPGA simulation platform. Those numbers show throughput doubling, power consumption at a fraction of the H200's, and cost improving several-fold as throughput and power efficiency gains flow through.

FPGA simulation validates architectural feasibility, which is not the same as post-tape-out performance under real workloads — an unavoidable caveat in reading those numbers.

On the Software Side, CUDA Is the Hurdle

Beyond hardware, Yizhu has assembled a full software stack: a proprietary ISA, a hardware-software co-designed architecture, heterogeneous fused computing IP, a CUDA-compatible compiler, operator libraries and a computing power networking system.

At the solution level, it supports three capabilities tied directly to current large-model workloads: a 1M ultra-long context window (roughly 1 million tokens), mixed-precision and MoE sparse computation, and cluster-level KV cache pooling, aimed at long-text workloads such as agents.

For a chip company taking a non-GPU route, CUDA compatibility is close to non-negotiable — the lower the cost of migrating off the incumbent ecosystem, the more likely customers are to give it a try.

No Consensus on Memory Medium, and the Contest Is Just Starting

Compute-in-memory is becoming a new consensus in the AI chip industry, but companies are not converging on the same memory medium.

Each medium carries its own trade-offs:

  • SRAM is mature and can reuse existing CMOS production lines, but it is area-hungry and capacity-limited.
  • ReRAM is non-volatile and dense, but production line maturity and resistance stability remain challenges.
  • 3D DRAM offers high bandwidth and large capacity, close to what mainstream AI inference requires, but it depends on advanced packaging and is not cheap.
  • HBF, leaning on flash capacity and cost advantages, slots into the memory hierarchy for large-model inference.

In other words, the field has yet to settle on a single answer, and Yizhu is betting on 3D DRAM.

The challenges on that path are just as concrete: the CUDA ecosystem moat, precision loss in analog compute-in-memory, the production maturity of the memory medium and the cost of advanced packaging will all shape whether the technology can complete the final stretch from tape-out to volume shipments.